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ds026 (v3.0) november 12, 2001 www.xilinx.com 1 product specification 1-800-255-7778 ? 2001 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? in-system programmable 3.3v proms for configuration of xilinx fpgas - endurance of 20,000 program/erase cycles - program/erase over full commercial/industrial voltage and temperature range ieee std 1149.1 boundary-scan (jtag) support simple interface to the fpga cascadable for storing longer or multiple bitstreams low-power advanced cmos flash process dual configuration modes - serial slow/fast configuration (up to 33 mhz) - parallel (up to 264 mb/s at 33 mhz) 5v tolerant i/o pins accept 5v, 3.3v and 2.5v signals 3.3v or 2.5v output capability available in pc20, so20, pc44 and vq44 packages design support using the xilinx alliance and foundation series software packages. jtag command initiation of standard fpga configuration description xilinx introduces the xc18v00 series of in-system program- mable configuration proms ( figure 1 ). initial devices in this 3.3v family are a 4-megabit, a 2-megabit, a 1-megabit, a 512-kbit, and a 256-kbit prom that provide an easy-to-use, cost-effective method for re-programming and storing large xilinx fpga or cpld configuration bitstreams. when the fpga is in master serial mode, it generates a configuration clock that drives the prom. a short access time after the rising cclk, data is available on the prom data (d0) pin that is connected to the fpga d in pin. the fpga generates the appropriate number of clock pulses to complete the configuration. when the fpga is in slave serial mode, the prom and the fpga are clocked by an external clock. when the fpga is in slave-parallel or selectmap mode, an external oscillator generates the configuration clock that drives the prom and the fpga. after the rising cclk edge, data are available on the proms data (d0-d7) pins. the data is clocked into the fpga on the following rising edge of the cclk. neither slave-parallel nor selectmap utilize a length count, so a free-running oscillator can be used. multiple devices can be concatenated by using the ceo output to drive the ce input of the following device. the clock inputs and the data outputs of all proms in this chain are interconnected. all devices are compatible and can be cascaded with other members of the family or with the xc17v00 one-time programmable serial prom family. 0 xc18v00 series of in-system programmable configuration proms ds026 (v3.0) november 12, 2001 00 product specification r figure 1: xc18v00 series block diagram control and jtag interface memory serial or parallel interface d0 data (serial or parallel [slave-parallel/selectmap] mode) d[1:7] slave-parallel and selectmap interface data address clk ce tck tms tdi tdo oe/reset ceo data ds026_01_111201 7 cf
xc18v00 series of in-system programmable configuration proms 2 www.xilinx.com ds026 (v3.0) november 12, 2001 1-800-255-7778 product specification r pinout and pin description table 1: pin names and descriptions (pins not listed are ?no connect?) pin name boundary scan order function pin description 44-pin vqfp 44-pin plcc 20-pin soic and plcc d0 4 data out d0 is the data output pin to provide data for configuring an fpga in serial mode. 40 2 1 3output enable d1 6 data out d0-d7 are the output pins to provide parallel data for configuring a xilinx fpga in slave-parallel/selectmap mode. 29 35 16 5output enable d2 2 data out 42 4 2 1output enable d3 8 data out 27 33 15 7output enable d4 24 data out 9 15 7 (1) 23 output enable d5 10 data out 25 31 14 9output enable d6 17 data out 14 20 9 16 output enable d7 14 data out 19 25 12 13 output enable clk 0 data in each rising edge on the clk input increments the internal address counter if both ce is low and oe/reset is high. 43 5 3 oe/ reset 20 data in when low, this input holds the address counter reset and the data output is in a high-impedance state. this is a bidirectional open-drain pin that is held low while the prom is reset. polarity is not programmable. 13 19 8 19 data out 18 output enable ce 15 data in when ce is high, this pin puts the device into standby mode and resets the address counter. the data output pin is in a high-impedance state, and the device is in low power standby mode. 15 21 10
xc18v00 series of in-system programmable configuration proms ds026 (v3.0) november 12, 2001 www.xilinx.com 3 product specification 1-800-255-7778 r cf 22 data out allows jtag config instruction to initiate fpga configuration without powering down fpga. this is an open-drain output that is pulsed low by the jtag config command. 10 16 7 (1) 21 output enable ceo 11 data out chip enable output (ceo ) is connected to the ce input of the next prom in the chain. this output is low when ce is low and oe/reset input is high, and the internal address counter has been incremented beyond its terminal count (tc) value. when oe/reset goes low, ceo stays high until the prom is brought out of reset by bringing oe/reset high. 21 27 13 12 output enable gnd gnd is the ground connection. 6, 18, 28 & 41 3, 12, 24 & 34 11 tms mode select the state of tms on the rising edge of tck determines the state transitions at the test access port (tap) controller. tms has an internal 50k ohm resistive pull-up on it to provide a logic ? 1 ? to the device if the pin is not driven. 511 5 tck clock this pin is the jtag test clock. it sequences the tap controller and all the jtag test and programming electronics. 713 6 tdi data in this pin is the serial input to all jtag instruction and data registers. tdi has an internal 50k ohm resistive pull-up on it to provide a logic ? 1 ? to the system if the pin is not driven. 39 4 tdo data out this pin is the serial output for all jtag instruction and data registers. tdo has an internal 50k ohm resistive pull-up on it to provide a logic ? 1 ? to the system if the pin is not driven. 31 37 17 v cc positive 3.3v supply voltage for internal logic and input buffers. 17, 35 & 38 23, 41 & 44 18 & 20 v cco positive 3.3v or 2.5v supply voltage connected to the output voltage drivers. 8, 16, 26 & 36 14, 22, 32 & 42 19 notes: 1. pin 7 is cf in serial mode, d4 in slave-parallel mode for 20-pin packages. table 1: pin names and descriptions (pins not listed are ? no connect ? ) (continued) pin name boundary scan order function pin description 44-pin vqfp 44-pin plcc 20-pin soic and plcc
xc18v00 series of in-system programmable configuration proms 4 www.xilinx.com ds026 (v3.0) november 12, 2001 1-800-255-7778 product specification r xilinx fpgas and compatible proms ta b l e 2 provides a list of xilinx fpgas and compatible proms. capacity in-system programming in-system programmable proms can be programmed indi- vidually, or two or more can be daisy-chained together and programmed in-system via the standard 4-pin jtag proto- col as shown in figure 2 . in-system programming offers quick and efficient design iterations and eliminates unnec- essary package handling or socketing of devices. the xilinx development system provides the programming data sequence using either xilinx jtag programmer software and a download cable, a third-party jtag development sys- tem, a jtag-compatible board tester, or a simple micropro- cessor interface that emulates the jtag instruction sequence. the jtag programmer software also outputs table 2: xilinx fpgas and compatible proms device configuration bits xc18v00 solution xc2v40 360,160 xc18v512 xc2v80 635,360 xc18v01 xc2v250 1,697,248 xc18v02 xc2v500 2,761,952 xc18v04 xc2v1000 4,082,656 xc18v04 xc2v1500 5,659,360 xc18v04 + xc18v02 xc2v2000 7,492,064 2 of xc18v04 xc2v3000 10,494,432 3 of xc18v04 xc2v4000 15,660,000 4 of xc18v04 xc2v6000 21,849,568 5 of xc18v04 + xc18v02 xc2v8000 29,063,136 7 of xc18v04 xcv50 559,200 xc18v01 xcv100 781,216 xc18v01 xcv150 1,040,096 xc18v01 xcv200 1,335,840 xc18v02 xcv300 1,751,808 xc18v02 xcv400 2,546,048 xc18v04 xcv600 3,607,968 xc18v04 xcv800 4,715,616 xc18v04 + xc18v512 xcv1000 6,127,744 xc18v04 + xc18v02 xcv50e 630,048 xc18v01 xcv100e 863,840 xc18v01 xcv200e 1,442,106 xc18v02 xcv300e 1,875,648 xc18v02 xcv400e 2,693,440 xc18v04 xcv405e 3,430,400 xc18v04 xcv600e 3,961,632 xc18v04 xcv812e 6,519,648 2 of xc18v04 xcv1000e 6,587,520 2 of xc18v04 xcv1600e 8,308,992 2 of xc18v04 xcv2000e 10,159,648 3 of xc18v04 xcv2600e 12,922,336 4 of xc18v04 xcv3200e 16,283,712 4 of xc18v04 xc2s15 197,696 xc18v256 xc2s30 336,768 xc18v512 xc2s50 559,200 xc18v01 xc2s100 781,216 xc18v01 xc2s150 1,040,096 xc18v01 xc2s200 1,335,840 xc18v02 xc2s50e 630,048 xc18v01 xc2s100e 863,840 xc18v01 xc2s150e 1,134,528 xc18v02 xc2s200e 1,442,016 xc18v02 xc2s300e 1,875,648 xc18v02 devices configuration bits xc18v04 4,194,304 xc18v02 2,097,152 xc18v01 1,048,576 xc18v512 524,288 xc18v256 262,144 ta b l e 2 : xilinx fpgas and compatible proms device configuration bits xc18v00 solution
xc18v00 series of in-system programmable configuration proms ds026 (v3.0) november 12, 2001 www.xilinx.com 5 product specification 1-800-255-7778 r serial vector format (svf) files for use with any tools that accept svf format and with automatic test equipment. all outputs are held in a high-impedance state or held at clamp levels during in-system programming. oe/reset the isp programming algorithm requires issuance of a reset that causes oe to go low. external programming xilinx reprogrammable proms can also be programmed by the xilinx hw-130 device programmer. this provides the added flexibility of using pre-programmed devices in board design and boundary-scan manufacturing tools, with an in-system programmable option for future enhancements and design changes. reliability and endurance xilinx in-system programmable products provide a guaran- teed endurance level of 20,000 in-system program/erase cycles and a minimum data retention of 20 years. each device meets all functional, performance, and data retention specifications within this endurance limit. design security the xilinx in-system programmable prom devices incorpo- rate advanced data security features to fully protect the pro- gramming data against unauthorized reading. ta b l e 3 shows the security setting available. the read security bit can be set by the user to prevent the internal programming pattern from being read or copied via jtag. when set, it allows device erase. erasing the entire device is the only way to reset the read security bit. ta b l e 3 : data security options ieee 1149.1 boundary-scan (jtag) the xc18v00 family is fully compliant with the ieee std. 1149.1 boundary-scan, also known as jtag. a test access port (tap) and registers are provided to support all required boundary scan instructions, as well as many of the optional instructions specified by ieee std. 1149.1. in addi- tion, the jtag interface is used to implement in-system pro- gramming (isp) to facilitate configuration, erasure, and verification operations on the xc18v00 device. ta b l e 4 lists the required and optional boundary-scan instructions supported in the xc18v00. refer to the ieee std. 1149.1 specification for a complete description of boundary-scan architecture and the required and optional instructions. default = reset set read allowed program/erase allowed read inhibited via jtag erase allowed figure 2: in-system programming operation (a) solder device to pcb and (b) program using download cable ds026_02_011100 gnd v cc (a) (b)
xc18v00 series of in-system programmable configuration proms 6 www.xilinx.com ds026 (v3.0) november 12, 2001 1-800-255-7778 product specification r instruction register the instruction register (ir) for the xc18v00 is eight bits wide and is connected between tdi and tdo during an instruction scan sequence. in preparation for an instruction scan sequence, the instruction register is parallel loaded with a fixed instruction capture pattern. this pattern is shifted out onto tdo (lsb first), while an instruction is shifted into the instruction register from tdi. the detailed composition of the instruction capture pattern is illustrated in figure 3 . the isp status field, ir(4), contains logic ? 1 ? if the device is currently in isp mode; otherwise, it contains logic ? 0 ? . the security field, ir(3), contains logic ? 1 ? if the device has been programmed with the security option turned on; otherwise, it contains logic ? 0 ? . boundary scan register the boundary-scan register is used to control and observe the state of the device pins during the extest, sam- ple/preload, and clamp instructions. each output pin on the xc18v00 has two register stages that contribute to the boundary-scan register, while each input pin only has one register stage. for each output pin, the register stage nearest to tdi con- trols and observes the output state, and the second stage closest to tdo controls and observes the high-z enable state of the pin. for each input pin, the register stage controls and observes the input state of the pin. identification registers the idcode is a fixed, vendor-assigned value that is used to electrically identify the manufacturer and type of the device being addressed. the idcode register is 32 bits wide. the idcode register can be shifted out for examina- tion by using the idcode instruction. the idcode is avail- able to any other system component via jtag. the idcode register has the following binary format: vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1 where v = the die version number f = the family code (50h for xc18v00 family) a = the isp prom product id (26h for the xc18v04) c = the company code (49h for xilinx) note: the lsb of the idcode register is always read as logic ? 1 ? as defined by ieee std. 1149.1 ta b l e 5 lists the idcode register values for the xc18v00 devices. the usercode instruction gives access to a 32-bit user programmable scratch pad typically used to supply informa- tion about the device ? s programmed contents. by using the usercode instruction, a user-programmable identifica- tion code can be shifted out for examination. this code is loaded into the usercode register during programming of the xc18v00 device. if the device is blank or was not loaded during programming, the usercode register con- tains ffffffffh. table 4: boundary scan instructions boundary-scan command binary code [7:0] description required instructions bypass 11111111 enables bypass sample/ preload 00000001 enables boundary-scan sample/preload operation extest 00000000 enables boundary-scan extest operation optional instructions clamp 11111010 enables boundary-scan clamp operation highz 11111100 all outputs in high-impedance state simultaneously idcode 11111110 enables shifting out 32-bit idcode usercode 11111101 enables shifting out 32-bit usercode xc18v00 specific instructions config 11101110 initiates fpga configuration by pulsing cf pin low ir[7:5] ir[4] ir[3] ir[2] ir[1:0] tdi-> 0 0 0 isp status security 0 0 1 ->td o notes: 1. ir(1:0) = 01 is specified by ieee std. 1149.1 figure 3: instruction register values loaded into ir as part of an instruction scan sequence ta b l e 5 : idcodes assigned to xc18v00 devices isp-prom idcode xc18v01 05024093h xc18v02 05025093h xc18v04 05026093h xc18v256 05022093h xc18v512 05023093h
xc18v00 series of in-system programmable configuration proms ds026 (v3.0) november 12, 2001 www.xilinx.com 7 product specification 1-800-255-7778 r xc18v00 tap characteristics the xc18v00 family performs both in-system programming and ieee 1149.1 boundary-scan (jtag) testing via a single 4-wire test access port (tap). this simplifies system designs and allows standard automatic test equipment to perform both functions. the ac characteristics of the xc18v00 tap are described as follows. tap timing figure 4 shows the timing relationships of the tap signals. these tap timing characteristics are identical for both boundary-scan and isp operations. tap ac parameters ta b l e 6 shows the timing parameters for the tap waveforms shown in figure 4 connecting configuration proms connecting the fpga device with the configuration prom (see figure 6 ). the data output(s) of the prom(s) drives the d in input of the lead fpga device. the master fpga cclk output drives the clk input(s) of the prom(s) (in master serial mode only). the ceo output of a prom drives the ce input of the next prom in a daisy chain (if any). the oe/reset input of all proms is best driven by the init output of the lead fpga device. this connection assures that the prom address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a v cc glitch. the prom ce input can be driven from the done pin. the ce input of the first (or only) prom can be driven by the done output of the first fpga device, provided that done is not permanently grounded. ce can also be permanently tied low, but this keeps the data output active and causes an unnecessary supply current of 10 ma maximum. slave-parallel/selectmap mode is similar to slave serial mode. the data is clocked out of the prom one byte per cclk instead of one bit per cclk cycle. see fpga data sheets for special configuration requirements. figure 4: test access port timing table 6: test access port timing parameters symbol parameter min max units t ckmin1 tck minimum clock period 100 - ns t ckmin2 tck minimum clock period, bypass mode 50 - ns t mss tms setup time 10 - ns t msh tms hold time 25 - ns t dis tdi setup time 10 - ns t dih tdi hold time 25 - ns t dov tdo valid delay - 25 ns tck t ckmin t mss tms tdi tdo t msh t dih t dov t dis ds026_04_020300
xc18v00 series of in-system programmable configuration proms 8 www.xilinx.com ds026 (v3.0) november 12, 2001 1-800-255-7778 product specification r initiating fpga configuration the xc18v00 devices incorporate a pin named cf that is controllable through the jtag config instruction. execut- ing the config instruction through jtag pulses the cf low for 300-500 ns, which resets the fpga and initiates config- uration. the cf pin must be connected to the program pin on the fpga(s) to use this feature. the jtag programmer software can also issue a jtag config command to initiate fpga configuration through the ? load fpga ? setting. selecting configuration modes the xc18v00 accommodates serial and parallel methods of configuration. the configuration modes are selectable through a user control register in the xc18v00 device. this control register is accessible through jtag, and is set using the ? parallel mode ? setting on the xilinx jtag programmer software. serial output is the default programming mode. master serial mode summary the i/o and logic functions of the configurable logic block (clb) and their associated interconnections are established by a configuration program. the program is loaded either automatically upon power up, or on command, depending on the state of the three fpga mode pins. in master serial mode, the fpga automatically loads the configuration pro- gram from an external memory. xilinx proms are designed to accommodate the master serial mode. upon power-up or reconfiguration, an fpga enters the mas- ter serial mode whenever all three of the fpga mode-select pins are low (m0=0, m1=0, m2=0). data is read from the prom sequentially on a single data line. synchronization is provided by the rising edge of the temporary signal cclk, which is generated by the fpga during configuration. master serial mode provides a simple configuration inter- face. only a serial data line, a clock line, and two control lines are required to configure an fpga. data from the prom is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of cclk. if the user-programmable, dual-function d in pin on the fpga is used only for configu- ration, it must still be held at a defined level during normal operation. the xilinx fpga families take care of this auto- matically with an on-chip pull-up resistor. cascading configuration proms for multiple fpgas configured as a serial daisy-chain, or a single fpga requiring larger configuration memories in a serial or selectmap configuration mode, cascaded proms provide additional memory ( figure 5 ). multiple xc18v00 devices can be concatenated by using the ceo output to drive the ce input of the downstream device. the clock inputs and the data outputs of all xc18v00 devices in the chain are interconnected. after the last bit from the first prom is read, the next clock signal to the prom asserts its ceo output low and drives its data line to a high-imped- ance state. the second prom recognizes the low level on its ce input and enables its data output. see figure 6 . after configuration is complete, address counters of all cas- caded proms are reset if the prom oe/reset pin goes low.
xc18v00 series of in-system programmable configuration proms ds026 (v3.0) november 12, 2001 www.xilinx.com 9 product specification 1-800-255-7778 r figure 5: jtag chain for configuring devices in master serial mode 4.7k 4.7k ** 1 2 3 4 tdo dout tdi tms tck vcc vcc din cclk done init vcc mode pins* xilinx fpga master serial vcc d0 vcco tdi clk tms ce tck ceo oe/reset program tdo tdi tms tck din cclk done init vcc mode pins* xilinx fpga slave serial program cf tdo gnd * for mode pin connections, refer to appropriate fpga data sheet. ** virtex, virtex-e is 300 ohms, all others are 4.7k. xc18v00 cascaded prom tdi tms tck tdo j1 ds026_08_011501 vcc vcco vcco vcc d0 vcco tdi clk tms ce tck ceo oe/reset cf tdo gnd xc18v00 first prom vcc
xc18v00 series of in-system programmable configuration proms 10 www.xilinx.com ds026 (v3.0) november 12, 2001 1-800-255-7778 product specification r figure 6: (a) master serial mode (b) virtex selectmap mode (c) spartan-ii/iie slave-parallel mode (dotted lines indicate optional connection) program din cclk init done first prom data ceo clk ce optional slave fpgas with identical configurations vcc fpga (low resets the address pointer) v cc v cco optional daisy-chained fpgas with different configurations oe/reset dout modes vcco cf program virtex select map busy cs write init d[0:7] cclk done virtex selectmap mode ce modes nc 3.3v external osc v cc 4.7k v cc ** v cc 3.3k v cc 3.3k v cc 1k i/o m0 m1 cs program spartan-ii, spartan- iie done init xc18vxx ceo ce oe/reset spartan-ii/iie slave-parallel mode master serial mode 8 cf clk d[0:7] d[0:7] cclk m0 m1 cs program optional daisy-chained spartan-ii, spartan-iie dout done init d[0:7] cclk 8 to additional optional daisy-chained devices to additional optional daisy-chained devices external osc i/o 1k (1) cs and write must be pulled down to be used as i/o. one option is shown. (2) virtex, virtex-e is 300 ohms, all others are 4.7k. (3) for mode pin connections, refer to the appropriate fpga data sheet. (4) external oscillator required for virtex/e selectmap or virtex-ii slave selectmap modes. ds026_05_111201 (1) for mode pin connections, refer to the appropriate fpga data sheet. (2) virtex is 300 ohms. cascaded prom data clk ce oe/reset cf clk d[0:7] oe/reset xc18vxx cf ceo v cc v cco v cc v cco v cco v cc v cco v cc cs(0) v cc (2) (1) 4.7k (1) (1) (2) (4) ce 4.7k v cc v cc 3.3k clk d[0:7] oe/reset xc18vxx cf ceo v cc v cco v cc v cco v cc cs(1) v cc
xc18v00 series of in-system programmable configuration proms ds026 (v3.0) november 12, 2001 www.xilinx.com 11 product specification 1-800-255-7778 r 5v tolerant i/os the i/os on each re-programmable prom are fully 5v tol- erant even through the core power supply is 3.3v. this allows 5v cmos signals to connect directly to the prom inputs without damage. in addition, the 3.3v v cc power supply can be applied before or after 5v signals are applied to the i/os. in mixed 5v/3.3v/2.5v systems, the user pins, the core power supply (v cc ), and the output power supply (v cco ) can have power applied in any order. this makes the prom devices immune to power supply sequencing issues. reset activation on power up, oe/reset is held low until the xc18v00 is active (1 ms) and able to supply data after receiving a cclk pulse from the fpga. oe/reset is connected to an exter- nal resistor to pull oe/reset high releasing the fpga init and allowing configuration to begin. oe/reset is held low until the xc18v00 voltage reaches the operating volt- age range. if the power drops below 2.0v, the prom resets. oe/reset polarity is not programmable. standby mode the prom enters a low-power standby mode whenever ce is asserted high. the output remains in a high-impedance state regardless of the state of the oe input. jtag pins tms, tdi and tdo can be in a high-impedance state or high. customer control pins the xc18v00 proms have various control bits accessible by the customer. these can be set after the array has been programmed using ? skip user array ? in xilinx jtag pro- grammer software. table 7: truth table for prom control inputs control inputs internal address outputs oe/reset ce data ceo i cc high low if address < tc (1) : increment if address > tc (1) : don ? t change active high-z high low active reduced low low held reset high-z high active high high held reset high-z high standby low high held reset high-z high standby notes: 1. tc = terminal count = highest address value. tc + 1 = address 0.
xc18v00 series of in-system programmable configuration proms 12 www.xilinx.com ds026 (v3.0) november 12, 2001 1-800-255-7778 product specification r absolute maximum ratings (1,2) recommended operating conditions quality and reliability characteristics symbol description value units v cc supply voltage relative to gnd ? 0.5 to +4.0 v v in input voltage with respect to gnd ? 0.5 to +5.5 v v ts voltage applied to high-z output ? 0.5 to +5.5 v t stg storage temperature (ambient) ? 65 to +150 p c t sol maximum soldering temperature (10s @ 1/16 in.) +260 p c t j junction temperature +150 p c notes: 1. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easier to achieve. during transitions, the device pins can undershoot to ? 2.0v or overshoot to +7.0v, provided this over- or undershoot lasts less then 10 ns and with the forcing current being limited to 200 ma. 2. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating condi tions is not implied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. symbol parameter min max units v ccint internal voltage supply (t a = 0 p c to +70 p c) commercial 3.0 3.6 v internal voltage supply (t a = ? 40 p c to +85 p c) industrial 3.0 3.6 v v cco supply voltage for output drivers for 3.3v operation 3.0 3.6 v supply voltage for output drivers for 2.5v operation 2.3 2.7 v v il low-level input voltage 0 0.8 v v ih high-level input voltage 2.0 5.5 v v o output voltage 0 v cco v t vcc v cc rise time from 0v to nominal voltage (1) 150ms notes: 1. at power up, the device requires the v cc power supply to monotonically rise from 0v to nominal voltage within the specified v cc rise time. if the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. symbol description min max units t dr data retention 20 - years n pe program/erase cycles (endurance) 20,000 - cycles v esd electrostatic discharge (esd) 2,000 - volts
xc18v00 series of in-system programmable configuration proms ds026 (v3.0) november 12, 2001 www.xilinx.com 13 product specification 1-800-255-7778 r dc characteristics over operating conditions symbol parameter test conditions min max units v oh high-level output voltage for 3.3v outputs i oh = ? 4 ma 2.4 - v high-level output voltage for 2.5v outputs i oh = ? 500 n a 90% v cco -v v ol low-level output voltage for 3.3v outputs i ol = 8 ma - 0.4 v low-level output voltage for 2.5v outputs i ol = 500 n a-0.4v i cc supply current, active mode 25 mhz - 25 ma i ccs supply current, standby mode - 10 ma i ilj jtag pins tms, tdi, and tdo v cc = max v in = gnd ? 100 - n a i il input leakage current v cc = max v in = gnd or v cc ? 10 10 n a i ih input and output high-z leakage current v cc = max v in = gnd or v cc ? 10 10 n a c in and c out input and output capacitance v in = gnd f = 1.0 mhz -10pf notes: 1. 18v01/18v512/18v256 only, cascadable. 2. 18v01/18v512/18v256 only, non-cascadable, no brown-out protection.
xc18v00 series of in-system programmable configuration proms 14 www.xilinx.com ds026 (v3.0) november 12, 2001 1-800-255-7778 product specification r ac characteristics over operating conditions for xc18v04 and xc18v02 oe/reset ce clk data t ce t oe t lc t sce t hce t hoe t cac t oh t df t oh t hc ds026_06_012000 t cyc symbol description min max units t oe oe/reset to data delay - 10 ns t ce ce to data delay - 20 ns t cac clk to data delay - 20 ns t oh data hold from ce , oe/reset , or clk 0 - ns t df ce or oe/reset to data float delay (2) -25ns t cyc clock periods 50 - ns t lc clk low time (3) 10 - ns t hc clk high time (3) 10 - ns t sce ce setup time to clk (to guarantee proper counting) (3) 25 - ns t hce ce high time (to guarantee proper counting) 2 - n s t hoe oe/reset hold time (guarantees counters are reset) 25 - ns notes: 1. ac test load = 50 pf. 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 5. if t hce high < 2 n s, t ce = 2 n s.
xc18v00 series of in-system programmable configuration proms ds026 (v3.0) november 12, 2001 www.xilinx.com 15 product specification 1-800-255-7778 r ac characteristics over operating conditions for xc18v01, xc18v512, and xc18v256 oe/reset ce clk data t ce t oe t lc t sce t hce t hoe t cac t oh t df t oh t hc ds026_06_012000 t cyc symbol description min max units t oe oe/reset to data delay - 10 ns t ce ce to data delay - 15 ns t cac clk to data delay - 15 ns t oh data hold from ce , oe/reset , or clk 0 - ns t df ce or oe/reset to data float delay (2) -25ns t cyc clock periods 30 - ns t lc clk low time (3) 10 - ns t hc clk high time (3) 10 - ns t sce ce setup time to clk (to guarantee proper counting) (3) 20 - ns t hce ce hold time to clk (to guarantee proper counting) 2 - n s t hoe oe/reset hold time (guarantees counters are reset) 20 - ns notes: 1. ac test load = 50 pf. 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 5. if t hce high < 2 n s, t ce = 2 n s.
xc18v00 series of in-system programmable configuration proms 16 www.xilinx.com ds026 (v3.0) november 12, 2001 1-800-255-7778 product specification r ac characteristics over operating conditions when cascading for xc18v04 and xc18v02 clk data ce ceo first bit last bit t cdf ds026_07_020300 oe/reset t ock t ooe t oce symbol description min max units t cdf clk to data float delay (2,3) -25 ns t ock clk to ceo delay (3) -20 ns t oce ce to ceo delay (3) -20 ns t ooe oe/reset to ceo delay (3) -20 ns notes: 1. ac test load = 50 pf. 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v.
xc18v00 series of in-system programmable configuration proms ds026 (v3.0) november 12, 2001 www.xilinx.com 17 product specification 1-800-255-7778 r ac characteristics over operating conditions when cascading for xc18v01, xc18v512, and xc18v256 clk data ce ceo first bit last bit t cdf ds026_07_020300 oe/reset t ock t ooe t oce symbol description min max units t cdf clk to data float delay (2,3) -25 ns t ock clk to ceo delay (3) -20 ns t oce ce to ceo delay (3) -20 ns t ooe oe/reset to ceo delay (3) -20 ns notes: 1. ac test load = 50 pf. 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v.
xc18v00 series of in-system programmable configuration proms 18 www.xilinx.com ds026 (v3.0) november 12, 2001 1-800-255-7778 product specification r ordering information valid ordering combinations marking information xc18v04vq44c xc18v02vq44c xc18v01vq44c xc18v512vq44c xc18v256vq44c xc18v04pc44c xc18v02pc44c xc18v01pc20c xc18v512pc20c xc18v256pc20c xc18v01so20c xc18v512so20c xc18v256so20c xc18v04vq44i xc18v02vq44i xc18v01vq44i xc18v512vq44i xc18v256vq44i xc18v04pc44i xc18v02pc44i xc18v01pc20i xc18v512pc20i xc18v256pc20i xc18v01so20i xc18v512so20i xc18v256so20i xc18v04 vq44 c operating range/processing c= commercial (t a = 0 p to +70 p c) i = industrial (t a = ? 40 p to +85 p c) package type vq44 = 44-pin plastic quad flat package pc44 = 44-pin plastic chip carrier (1) so20 = 20-pin small-outline package (2) pc20 = 20-pin plastic leaded chip carrier (2) device number xc18v04 xc18v02 xc18v01 xc18v512 xc18v256 notes: 1. xc18v04 and xc18v02 only. 2. xc18v01, xc18v512, and xc18v256 only. 20-pin package (1) due to the small size of the commercial serial prom packages, the complete ordering part number cannot be marked on the package. the xc prefix is deleted and the package code is simplified. device marking is as follows: 44-pin package xc18v04 vq44 c operating range/processing c= commercial (t a = 0 p to +70 p c) i = industrial (t a = ? 40 p to +85 p c) package type vq44 = 44-pin plastic quad flat package pc44 = 44-pin plastic leaded chip carrier (1) notes: 1. xc18v02 and xc18v04 only. device number xc18v04 xc18v02 xc18v01 xc18v512 xc18v256 18v01 s c operating range/processing c = commercial (t a = 0 p to +70 p c) i = industrial (t a = ? 40 p to +85 p c) package type s20 = 20-pin small-outline package j20 = 20-pin plastic leaded chip carrier device number 18v01 18v512 18v256 notes: 1. xc18v01, xc18v512, and xc18v256 only.
xc18v00 series of in-system programmable configuration proms ds026 (v3.0) november 12, 2001 www.xilinx.com 19 product specification 1-800-255-7778 r revision history the following table shows the revision history for this document. date version revision 2/9/99 1.0 first publication of this early access specification 8/23/99 1.1 edited text, changed marking, added cf and parallel load 9/1/99 1.2 corrected jtag order, security and endurance data. 9/16/99 1.3 corrected selectmap diagram, control inputs, reset polarity. added jtag and cf description, 256 kbit and 128 kbit devices. 01/20/00 2.0 added q44 package, changed xc18xx to xc18vxx 02/18/00 2.1 updated jtag configuration, ac and dc characteristics 04/04/00 2.2 removed stand alone resistor on init pin in figure 5. added virtex-e and em parts to fpga table. 06/29/00 2.3 removed xc18v128 and updated format. added ac characteristics for xc18v01, xc18v512, and xc18v256 densities. 11/13/00 2.4 features: changed 264 mhz to 264 mb/s at 33 mhz; ac spec.: t sce units to ns, t hce ce high time units to n s. removed standby mode statement: ? the lower power standby modes available on some xc18v00 devices are set by the user in the programming software ? . changed 10,000 cycles endurance to 20,000 cycles. 01/15/01 2.5 updated figures 5 and 6, added 4.7 resistors. identification registers: changes isp prom product id from 06h to 26h. 04/04/01 2.6 updated figure 6 , virtex selectmap mode; added xc2v products to compatible prom table; changed endurance from 10,000 cycles, 10 years to 20,000, 20 years; 04/30/01 2.7 updated figure 6 : removed virtex-e in note 2, fixed selectmap mode connections. under ac characteristics over operating conditions for xc18v04 and xc18v02 , changed t sce from 25 ms to 25 ns. 06/11/01 2.8 ac characteristics over operating conditions for xc18v01, xc18v512, and xc18v256 changed min values for t sce from 20 ms to 20 ns and for t hce from 2 ms to 2 n s. 09/28/01 2.9 changed the boundary scan order for the ceo pin in ta b l e 1 , updated the configuration bits values in the table under xilinx fpgas and compatible proms , and added information to the recommended operating conditions table. 11/12/01 3.0 updated for spartan-iie fpga family.

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